page 1 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 www.psemi.com rf1 rf2 rfc cmos control driver esd esd esd ctrl ctrl or v dd the pe42421 ultracmos ? rf switch is designed to cover a broad range of applications from 10 mhz through 3000 mhz. this reflective switch integrates on-board cmos control logic with a low voltage cmos-compatible control interface, and can be controlled using either single-pin or complementary control inputs. using a nominal +3-volt power supply voltage, a typical input 1 db compression point of +33.5 dbm can be achieved. the pe42421 spdt rf switch is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt ultracmos ? 10 mhz ? 3.0 ghz rf switch product description figure 1. functional diagram pe42421 features ?? single-pin or complementary cmos logic control inputs ?? low insertion loss: 0.35 db at 1000 mhz, 0.5 db at 2000 mhz ?? isolation of 30 db at 1000 mhz, 20 db at 2000 mhz ?? typical input 1 db compression point of +33.5 dbm ?? 1.8v minimum power supply voltage ?? sc-70 package figure 2. package 6-lead sc-70 71-0015-01 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 2 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 ultracmos ? rfic solutions notes: 1. device linearity will begin to degrade below 10 mhz 2. the dc transient at the output of any port of the switch w hen the control voltage is switched from low to high or high to low in a 50 ? test set-up, measured with 1ns risetime pulses and 500 mhz bandwidth 3. a tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. see figure 6 for details table 1. electrical specifications @ +25c, v dd = 3v (z s = z l = 50? ) parameter condition minimum typical maximum unit operation frequency 1 10 mhz 3000 mhz insertion loss 3 1000 mhz 2000 mhz 0.35 0.50 0.45 0.60 db db isolation 1000 mhz 2000 mhz 29 19 30 20 db db return loss 3 1000 mhz 2000 mhz 21 24 22 27 db db ?on? switching time 50% ctrl to 0.1 db of final value, 1 ghz 1.50 us ?off? switching time 50% ctrl to 25 db isolation, 1 ghz 1.50 us video feedthrough 2 15 mv pp input 1 db compression 1000 mhz @ 2.3 - 3.3v 1000 mhz @ 1.8 - 2.3v 2500 mhz @ 2.3 - 3.3v 2500 mhz @ 1.8 - 2.3v 31.5 29.5 28.5 28 33.5 30.5 30.5 29 dbm input ip3 1000 mhz, 20dbm input power 55 dbm logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 3 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 www.psemi.com table 2. pin descriptions electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. figure 3. pin configuration (top view) pin no. pin name description 1 rf1 4 rf port1 2 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 3 rf2 4 rf port2 4 ctrl switch control input, cmos logic level. 5 rfc 4 rf common 6 ctrl or v dd this pin supports tw o interface options: single-pin control mode . a nominal 3-volt supply connection is required. complementary-pin control mode . a com- plementary cmos control signal to ctrl is supplied to this pin. bypassing on this pin is not required in this mode. table 4. absolute maximum ratings notes: 5. to maintain optimum device performance, do not exceed max p in at desired operating frequency (see figure 4 ) symbol parameter/condition min max unit v dd power supply voltage -0.3 4.0 v v i voltage on any dc input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t op operating temperature range -40 85 c p in input power (50 ? ) +34 5 dbm v esd esd voltage (hbm, ml_std 883 method 3015.7) 2000 v esd voltage (mm, jedec, jesd22-a114-b) 100 v table 3. operating ranges parameter min typ max unit v dd power supply voltage 1.8 3.0 3.3 v i dd power supply current (v dd = 3v, v cntl = 3v) 9 20 a control voltage high 0.7x v dd v control voltage low 0.3x v dd v figure 4. maximum input power exceeding absolute maximum ratings may cause permanent damage. operati on should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. moisture sensitivity level the moisture sensitivity level rating for the pe42421 in the sc70 package is msl1. note: 4. all rf pins must be dc blocked with an external series capacitor or held at 0 v dc switching frequency the pe42421 has a maximum 25 khz switching rate. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 4 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 ultracmos ? rfic solutions control voltages signal path pin 6 (v dd ) = v dd pin 4 (ctrl) = high rfc to rf2 pin 6 (v dd ) = v dd pin 4 (ctrl) = low rfc to rf1 table 5. single-pin control logic truth table table 6. complementary-pin control logic truth table control voltages signal path pin 6 (ctrl or v dd ) = low pin 4 (ctrl) = high rfc to rf2 pin 6 (ctrl or v dd ) = high pin 4 (ctrl) = low rfc to rf1 control logic input the pe42421 is a versatile rf cmos switch that supports two operating control modes; single-pin control mode and complementary-pin control mode. single-pin control mode enables the switch to operate with a single control pin (pin 4) supporting a +3-volt cmos logic input, and requires a dedicated +3-volt power supply connection on pin 6 (v dd ). this mode of operation reduces the number of control lines required and simplifies the switch control interface typically derived from a cmos ? processor i/o port . complementary-pin control mode allows the switch to operate using complementary control pins ctrl and ctrl (pins 4 & 6), that can be directly driven by +3-volt cmos logic or a suitable ? processor i/o port. this enables the pe42421 to be used as a potential alternate source for spdt rf switch products used in positive control voltage mode and operating within the pe42421 operating limits. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 5 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 www.psemi.com t-line description -- mode l = cpwg h=28mils t=2.1mils w=47mils g=30mils er = 4.4 seeassynote 2 seeassynote 2 1 2 j7 cntl 1 j3 rf2 r1 1kohm r2 1kohm 1 j5 n/ a 1 j4 n/a 1 j2 rf1 1 2 j6 cntlx/vdd 2 gnd 1 rf_1 3 rf_2 4 ctrl 5 rfc 6 vdd u1 pe42421/sc70-6 1 j1 rfc 12 c1 0.5pf 12 c2 0.5pf evaluation kit the spdt switch ek board was designed to ease customer evaluation of peregrine?s pe42421. the rf common port is connected through a 50 ? transmission line via the top sma connector, j1. rf1 and rf2 are connected through 50 ? transmission lines via sma connectors j2 and j3, respectively. a through 50 ? transmission is available via sma connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.0476?, trace gaps of 0.030?, dielectric thickness of 0.028?, metal thickness of 0.0021? and r of 4.4. j6 and j7 provide a means for controlling dc and digital inputs to the device. j6-1 is connected to the device v dd or ctrl input. j7-1 is connected to the device ctrl input. figure 5. evaluation board layouts figure 6. evaluation board schematic peregrine specification 102-0756-01 peregrine specification 101-0162-02 notes: add two 0.5 pf caps in series to be shunted on the j1 sma input solder c1 side 1 to the rf trace close to the j1 pin solder c1 side 2 to c2 side 1 solder c2 side 2 to ground general comments transmission lines connected to j1, j2 , and j3 should have exactly the same electrical length the path from j2 to j3 including the distance through the part should have the same length as j4 and j5 and be in parallel to j4 to j5 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 6 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 ultracmos ? rfic solutions typical performance data @ -40c to 85c (unless otherwise noted) figure 7. insertion loss figure 8. isolation ? input to output figure 9. isolation ? output to output figure 10. return loss (input) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 7 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 www.psemi.com typical performance data @ v dd = 2.3v, t = 25c figure 11. insertion loss figure 12. isolation ? input to output figure 13. isolation ? output to output figure 14. return loss (input & output) logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 8 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 ultracmos ? rfic solutions figure 15. package drawing 6-lead sc-70 2.100.05 1.250.10 1.30 0.65 0.2250.075 2.100.10 0.900.10 0.050.05 top view side view end view a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) pin #1 corner recommended land pattern 1.90 0.65 0.50 min 1.30 0.40 min 13 6 4 0.360.10 0.1650.085 0.10 a b all features 181-0013 figure 16. top marking specification ? ppp yww = pin 1 indicator ppp = part number yww = date code 17-0021 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe42421 page 9 of 9 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0396-03 www.psemi.com table 7. ordering information order code part marking description package shipping method ek42421-01 pe42421-ek pe42421 evaluati on kit evaluation kit 1 / box pe42421scaa-z 421 pe42421 spdt rf switch green 6-lead sc-70 3000 units / t&r figure 17. tape and reel specifications pin 1 tape feed direction 1 2 3 4 5 6 1 2 3 4 5 6 device orientation in tape pin 1 top of device advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com . logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
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